This category covers mid-range, SOSA™-aligned 3U OpenVPX payload processing cards powered by Altera Agilex™ 5 E-Series SoC FPGAs (such as the A5E 065A / A5E 065B variants).
While top-tier Agilex 7 and Agilex 9 modules handle ultra-dense direct RF and heavy radar compute, Agilex 5 Payload Modules provide an optimal balance of power, performance, and thermal efficiency (SWaP-C). They act as primary compute nodes for edge AI, video analytics, software-defined radio (SDR), and real-time sensor processing inside power-constrained 3U VPX chassis.
Key Highlights
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Silicon Architecture (Agilex 5 E-Series):
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FPGA Fabric: Up to 656K Logic Elements with enhanced DSP blocks and Tensor-capable AI acceleration engines.
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Asymmetric Processing System (HPS): Heterogeneous multicore architecture featuring a Dual-core Arm® Cortex®-A76 (up to 1.8 GHz) alongside a Dual-core Arm® Cortex®-A55 (up to 1.5 GHz) running Linux and real-time control stacks.
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System Memory & Storage:
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HPS Memory: 2GB LPDDR4 with ECC dedicated to the Arm processing cluster .
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FPGA Memory: Dual independent 2GB LPDDR4 with ECC (4GB total) dedicated to the FPGA logic fabri c.
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Storage: Onboard 32GB eMMC (expandable to 128GB) + 1Gb QSPI Fla sh.
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Backplane & High-Speed Connectivity:
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Slot Profile: Compliant with SOSA payload profiles like
SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-*. -
Data & Expansion Planes: Supports 40GBASE-KR4, 10GBASE-KR, and PCIe Gen3 x4 / x8 channels across backplane connec tors.
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Optical & RF Interconnects: VITA 66.5 optical aperture (12-fiber MT Ferrule) or NanoRF connectors for high-speed fiber or analog sam pling.
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Built-in System Management: Tier-3 VITA 46.11 IPMC controller (Arm Cortex-M0+ based) for voltage, current, and thermal monitoring across the VPX c hassis.
Please find the detailed product information here:
Agilex™ 5 SOSA-aligned 3U VPX Plug-in Module (Payload Profile)