GEM0 and GEM3 are enabled and ported in the G60M Vivado design. Since these interfaces are part of the PS (Processing System) and use dedicated FPGA pins, there is no need to include them in the IO.xdc constraints file.
Also, as mentioned in G60D DevKit datasheet and carrier board schematics: GEM0 and GEM3 are connected to RJ45 Magjack of the DevKit carrier board.
Please check G60D Devkit datasheet and (carrier board) schematics for the identifiers.
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
ZU48/47/43/28/27/25DR RFSoC System on Module