In the Intel documentation, it is describe that on each tile, FGT transceivers clocking can be achieved by 10 different channels. Each one clocking specific quads into the tile. Example, the clock channel 0, which is supposed to (from intel documentation) be used to clock Quad 0 and Quad 1.
Yes, the clock on channel 0 can be used for both Quads 0 and 1. This has been updated in the upcoming revisions of the G43M Agilex7 SoC FPGA SOM Datasheet.
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Please find the detailed product information here:
Agilex™ 7 (R31A/R31B/R31C) SoC FPGA System on Module