In the iWave standard release; both, Internal PLL enabled design and Internal PLL disabled design are we provided.
Please use the Internal PLL RF-Analyzer design instead of attempting to enable the PLL at runtime in the RF-Analyzer tool with the design. The RF-Analyzer tool has certain limitations when enabling the PLL at runtime, as some clock, samples and sampling rate related parameters are fixed during design generation and may not be updated correctly through runtime configuration.
Test with the FPGA Design and Binaries available from the provided FTP link.
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
ZU49/ZU39/ZU29DR RFSoC System on Module