In the current design, the SDI pattern generator is controlled through PIO registers. The PIO IP (pattgen_ctrl_pio) is connected to the System Console via a JTAG-to-Avalon Master Bridge IP (pattgen_ctrl_master), which performs register writes using a TCL script.
To avoid using TCL and JTAG, consider the following options:
HPS-Based Control:
Connect the PIO (pattgen_ctrl_pio) to the HPS using the HPS-to-FPGA bridge and control it from a Linux application.
RTL-Based Control:
Remove the JTAG master and implement simple RTL logic (e.g., an FSM or fixed register values) to drive the PIO directly with the required configuration.
Both approaches eliminate the need for TCL and JTAG.
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Please find the detailed product information here:
Agilex™ 5 SoC FPGASystem on Module