The maximum memory clock frequency for LPDDR4 on Agilex® 5 depends on two key factors: the EMIF IP Clock Mode and your Device Speed Grade / Silicon Stepping.
1. EMIF IP Clock Mode (Synchronous vs. Asynchronous)
In Quartus Prime Pro, the clocking mode between the FPGA core fabric and the EMIF PHY defines the maximum achievable speed:
- Synchronous Mode (Fabric Direct-User Clock Synchronous to PHY):
The user fabric clock is tied directly to the memory clock (mem_CK / 8 for LPDDR4).
Due to internal timing constraints between the core and periphery, the maximum frequency is limited to 1066 MHz (2133 Mbps). - Asynchronous Mode (Fabric Direct-User Clock Asynchronous to PHY / AXI) The core fabric clock is decoupled from the memory clock using internal asynchronous bridges.
This allows the memory interface to run at its maximum rated speed of 1333 MHz (2667 Mbps).
2. Device Silicon Stepping & Speed Grade
Ensure your target device silicon supports 1333 MHz using EMIF Specification Estimator:
- Engineering Sample (ES0 / suffix ‘R’): Supports 1333 MHz only on Speed Grade 4.
- Production Silicon: Supports 1333 MHz on Speed Grade 5 and Speed Grade 4.
3. Current iWave Reference Design Note
- By default, the iWave Agilex 5 SOM reference design is set to Synchronous Mode (1066 MHz / 2133 Mbps).
- To achieve 1333 MHz (2667 Mbps):
Confirm your SOM carries silicon that meets the speed grade requirement (Speed Grade -4 for ES0, or Speed Grade -5/-4 for Production).
In the Quartus EMIF IP Parameter GUI, switch to Asynchronous Mode and set the memory frequency to 1333 MHz.
References:
- Altera EMIF Specification Estimator
- Agilex 5 EMIF IP User Guide: User Clock Access Modes
- Agilex 5 EMIF IP Release Notes
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
Agilex™ 5 SoC FPGASystem on Module