Regarding clock generation and its clock application note please connect with iWave representative for the FTP link. This document explains how to generate clocks using the TICS and AZURITE tools.
Applying the FSBL patch, please follow the procedures mentioned in section “Manual Yocto Build Procedure” of the Software User Guide for the BSP extraction.
The clocks are configured in the FSBL. Kindly refer to the FSBL patch available in the BSP from the FTP link and apply the same changes to Baremetal FSBL source code. Additionally, please add the following line in the psu_init.c file under the psu_init(void) function:
status &= ig60m_early_init();
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Please find the detailed product information here:
ZU48/47/43/28/27/25DR RFSoC System on Module