Is there any reference design for implementing display port TX link in a PL Design?

iWave has validated DisplayPort (DP) using a NIOS-based TPG example design. However, it cannot be implemented together with SGMII, as Bank 1C Channel 3 is shared between DP0 and SGMII. Supporting the DP interface would require additional hardware modifications. Kindly connect with iWave representative for modifications.

For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com

Please find the detailed product information here:
Agilex™ 5 SoC FPGASystem on Module