Q1. Is it possible to use the JTAG pins as general-purpose I/O (GPIO) to send or receive data when not programming?
Ans: No. On iG-G47M platform, the pins on 14-pin header of JTAG connector is from dedicated JTAG pin of Kintex™ UltraScale+™ FPGA and cannot be configured as GPIO.
Q2. Should SW6 be set to ‘01XX’ rather than ‘00XX’ when programming via the HS2 cable? Toggling the switch constantly is inconvenient.
Ans: The JTAG port on iG-G47M DevKit supports JTAG interface of both FPGA and LS1021A processor. To use the JTAG-HS2 cable, used for JTAG interface of Kintex™ UltraScale+™ FPGA SW6, position should be 00XX and 01XX state of SW6 is for LS1021A JTAG interface.
Q3. Suspecting the JTAG interface is not receiving a stable clock when the switch is in the “0011” configuration.
Ans: Reproduced the JTAG detection behavior issue specifically within Vivado 2024.1 Lab Edition. Testing indicates that this is a version-specific software issue rather than a hardware clock failure, as the behavior is not observed in other versions of the tool.
We recommend using Vivado Lab Edition 2024.2 (or a different stable release) to program the FPGA binaries.
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
Kintex™ UltraScale+™ System on Module