Below are the steps that need to follow exactly as per the 12G SDI OUT Test document to validate the 12G SDI OUT reference design. Kindly make sure you are referring to the 12G SDI OUT Test document while following these steps:
- Set the Boot Selection switches to JTAG-only mode
[OFF OFF OFF OFF] - Power ON the board and flash the JIC file to QSPI using JTAG.
This procedure ensures that the required clocks are properly programmed. - Power OFF the board and change the Boot Selection switches to Boot Mode (Active Serial Fast)
[OFF ON ON OFF]
Before testing, make sure the coresponding is OFF, this switch is located at the bottom of the carrier board. - Power ON the board and flash the SOF file to configure the FPGA.
- You may then continue the document to complete the SDI OUT testing procedure.
No TFTP, Linux host PC, or manual clock configuration is required for this test flow.
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Please find the detailed product information here:
Agilex™ 5 SoC FPGASystem on Module