The I/O voltage of PL HD Banks (PL Bank 45 & 46) are generated from PMIC LDO3 and by default set to 1.8V, this I/O voltage is configurable through software after bootup.
In FSBL we are configuring I/O voltage to 1.8V through config_pmic_ldo3() function in xfsbl_board.c file
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Please find the detailed product information here:
Zynq™ UltraScale+™ ZU7/ZU5/ZU4 MPSoC System on Module