What conditions must be met for the SYS_SYNC_CLK_IN signal to ensure proper clock generation before the Power-On Reset (POR) signal transitions to high?

Versal Boards & Solutions Versal™ AI Edge: VE2302
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By default, in G57M SYS_SYNC_CLK is not used to generate output clocks from SI5332A-D-GM1 clock generator.

If SYS_SYNC_CLK_IN is used as input to SI5332A-D-GM1 clock generator, then this clock should be generated along with SOM_PWR_EN or before POR goes high. And the estimated total time between SOM_PWR_EN and POR is 30ms.

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