The correct approach is replacing the FPGA .sof file with the custom design while retaining the provided .hex and uboot.bin files is the expected procedure.
Additional Verification Steps:
- Program the generated JIC file into the QSPI flash while the board is in JTAG Mode.
- After programming is complete, switch the board back to Active Serial Mode (Normal/Fast Mode) and power-cycle the board.
- Observe the U-Boot console messages during boot and verify whether the FPGA RBF file is being loaded successfully (as shown in the reference image provided).
Note: After generating a new FPGA design, please ensure that the corresponding custom RBF file is updated in the eMMC. Alternatively, manually load the RBF file from a USB drive by following the procedure described in the section referenced below.
If the FPGA RBF file is not being loaded during boot, please refer to Section “Linux Binary Programming to eMMC/SD” from the iG-RainboW-G43M Linux User Guide for FPGA core configuration instructions.
Once the FPGA has been configured with custom RBF file:
- Open Quartus project and the corresponding Signal Tap (.stp) file.
- Select the appropriate JTAG hardware (USB BLASTER II).
- In the Signal Tap window, ensure that the FPGA device is selected before starting the debug session.
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
Agilex™ 7 (R31A/R31B/R31C) SoC FPGA System on Module