The ZU49DR standard release FPGA design and the ZU49DR 100G Ethernet FPGA design has no changes.
However, when changing the device from ZU49DR R3.0 (-1 speed grade) to ZU49DR R3.3 (-2 speed grade), some device-specific parameters may be affected. These include DDR speed, PCIe generation support, RF sampling rates, and GT lane rates, which is needs to be updated accordingly to match the capabilities of the new device.
However, if the existing R3.0 configuration is used, it will not impact the performance of the device, when all operating parameters remain within the supported limits of the new device.
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
ZU49/ZU39/ZU29DR RFSoC System on Module