Based on the Agilex 5 EMIF Specification Estimator, for LPDDR4 interface on Agilex 5 E-Series Group B SoC, the maximum supported memory clock frequency depends on the selected clock mode.
The estimator shows:
- Asynchronous Clock Mode: Supports up to 1333 MHz memory clock frequency.
- Synchronous Clock Mode: Supports up to 1066 MHz memory clock frequency.
External Memory Interface (EMIF) Spec Estimator | Altera (https://www.altera.com/design/guidance/emif/emif-spec-estimator?deviceFamily=Agilex™+5+E-Series+Group+B+SoC&temperatureAndSpeedGrade=E5&memoryStandard=LPDDR4&interfaceType=Hard&memoryFormat=Component)
In the current EMIF IP configuration, the Main band Access Mode is set to “Fabric Direct - User Clock Synchronous to PHY”, which corresponds to Synchronous Clock Mode.
Therefore, the generated EMIF IP is limited to the synchronous-mode maximum frequency.
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Please find the detailed product information here:
Agilex 5 SoC FPGA System on Module