What is the Ref clock provided to the FPGA EMIF? And the clock rate of the DDR?

Agilex Boards & Solutions Agilex™ 7 R31A/B/C
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The Ref clock provided to the FPGA EMIF is 200MHz, this is to support a maximum Memory clock frequency of 1600MHz.
DDR supports a clock rate of 1600MHz.

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Agilex™ 7 (R31A/R31B/R31C) SoC FPGA System on Module