For USB 3.0 operation, a 100MHz reference clock is required. While validating USB 3.0 interface in Agilex 5 Devkit (G58D), the 100 MHz reference clock is generated by the carrier board’s ZL3073 clock synthesizer and connected through B2B-1 pins (D51/D52) to the SOM pins.
When B2B-1 pins are used to provide the required 100 MHz reference clock for the USB 3.0 interface, the PCIe endpoint cannot be supported, because the same 100MHz reference clock from the PCIe x4 connector is shared through B2B-1 pins.
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Please find the detailed product information here:
Agilex™ 5 SoC FPGASystem on Module