If the MMC still contains an older RBF file instead of the RBF generated from the latest Quartus compilation, the FPGA will not be configured with the expected design. In such a case, the “Error sending bitstream” message observed in the screenshot would be expected.
Please note that each time you compile a design in Quartus and generate a new SOF file, you should also generate a corresponding JIC file. Along with the JIC file, Quartus will generate a matching XXX.core.rbf file for that specific design.
As a verification step, if updating the RBF file in the MMC is not feasible, please manually load the newly generated RBF file from a USB drive through the U-Boot console and verify that the FPGA configures successfully with your custom design.
Procedure:
- Copy the newly generated XXX.core.rbf file to a USB drive and connect it to the setup.
- Set the board to Active Serial Mode (Normal/Fast Mode) and power on the system.
- Stop at the U-Boot console by pressing any key.
- Execute the following commands from Section “Linux Binary Programming to eMMC/SD” of the iG-RainboW-G43M Linux User Guide:
usb start
fatload usb 0:1 ${loadaddr} XXX.core.rbf ## Rename RBF file
fpga load 0 ${loadaddr} ${filesize}
bridge enable
If the FPGA image loads successfully, a successful FPGA configuration message is seen in the terminal. At that point, the FPGA will be running the custom design, and SignalTap verification can be proceeded.
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
Agilex™ 7 (R31A/R31B/R31C) SoC FPGA System on Module