This issue is due to a limitation of HDIO I/O banks. Since there are no Clock Management Tiles (CMTs), such as MMCMs or PLLs, in these clock regions, the clock input can connect to an MMCM or PLL only through a global buffer. Therefore, it is necessary to add the following BUFGCE instantiation in the top module:
// BUFGCE: General Clock Buffer with Clock Enable
BUFGCE #(
.CE_TYPE("SYNC"), // ASYNC, HARDSYNC, SYNC
.IS_CE_INVERTED(1'b0), // Programmable inversion on CE
.IS_I_INVERTED(1'b0), // Programmable inversion on I
.SIM_DEVICE("ULTRASCALE_PLUS") // ULTRASCALE, ULTRASCALE_PLUS
)
BUFGCE_inst (
.O(gty_sysclk_i), // 1-bit output: Buffer
.CE(1'b1), // 1-bit input: Buffer enable
.I(gty_sysclkp_i) // 1-bit input: Buffer
);
AMD also recommends the same. Please refer to the link below for more information:
[DRC PLHDIO-4] HDIO DRC Checks:
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Please find the detailed product information here:
ZU48/47/43/28/27/25DR RFSoC System on Module