The counters mapped to the registers that mentioned are incremented upon receiving a read request from the buffer (during write NVMe) or a write enable signal to the buffer (during read from NVMe). Each count represents 16 bytes (128 bits) of data.
DATA_TRANS_SIZE_U = holds the upper 32 bits of data transfer size
DATA_TRANS_SIZE_L = holds the lower 32bits of data transfer size
These registers are updated continuously based on the read request from the buffer (during write NVMe) or a write enable signal to the buffer (during read from NVMe) and the register values represents the corresponding count captured at the exact moment when the register read operation is performed.
These registers are intended for debug purposes and are printed in Tera Term to indicate the amount of data transferred.
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Please find the detailed product information here:
Agilex™ 7 (R31A/R31B/R31C) SoC FPGA System on Module