PCIe & Accelerator Cards RFSoC ZU48/ZU47/ZU43DR
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About the RFSoC ZU48/ZU47/ZU43DR category
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0 | 1 | May 15, 2026 |
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Why does the PS-GTR PCIe link negotiates at x2 despite the PS being configured for x4 in G60P ZU47DR?
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0 | 4 | June 23, 2026 |
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To which pin is DAC_REF_CLK_P/N_230 clock connected in G60P?
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0 | 3 | May 27, 2026 |
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Is G60P SOM pulling 3.24A with the total power drawn (FPGA & peripherals)?
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0 | 4 | May 27, 2026 |
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Can the baluns be changed for different frequency range in G60P?
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0 | 11 | April 9, 2026 |
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How are the FPGA IOs connected to the SMA connector and what is its signal level?
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0 | 7 | April 1, 2026 |
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How are the GTR lines configured in G60P RFSoC Development Kit?
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0 | 5 | April 1, 2026 |
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How is the CLKIN0_P signal coupling on the G60M SOM and what waveform is in the input?
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0 | 5 | April 1, 2026 |
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What are the footprint-compatible part numbers for 3.1 GHz to 5.8 GHz BALUN used in G60P?
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0 | 5 | March 23, 2026 |
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How iG-G60P Quad QSFP28/QSFP+ FMC+ module is validated with IBERT?
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0 | 9 | January 28, 2026 |