The MT8395 PCIe controller does not support SRNS (Separate Reference Clock, No SSC) or SRIS (Separate Reference Clock with Independent SSC).
The PCIe PHY is designed strictly for a Common Clock (CC) architecture. This requires a single, shared 100MHz (or 125MHz) differential reference clock between the Root Complex (RC) and the Endpoint (EP).
Since Root Complex (RC) cannot provide the clock to the Endpoint (EP), it is a must to use an external low-jitter clock generator or buffer on the board to distribute the same reference clock signal to both the MT8395 and the host Root Complex (RC).
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
MediaTek Genio 1200 OSM System on Module