The Ethernet port (SGMII) is connected through the EMAC0 interface of the Agilex 5 SoC FPGA (HPS to FPGA routed), with the Bank 1C transceiver channel-3 connected to the Ethernet PHY on the SOM.
Please refer to the following example design available from Altera, which demonstrates SGMII using transceivers:
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Please find the detailed product information here:
Agilex™ 5 SoC FPGASystem on Module