The ADC full swing and DAC output power information is mentioned in the attached “ADC-DAC-PWR.pdf”.
As mentioned in the Xilinx datasheet, the typical value for the ADC full-scale input is 1 Vppd with 1 dBm for a 5 MHz input tone (100Ω termination). The maximum output power for the DAC (signal frequency <200 MHz, 100Ω termination) is 6.5 dBm.
According to theoretical calculations, it is necessary to provide 0.7 Vpp and 1 dBm power at the SMA connector side (50Ω termination) to achieve full-scale ADC at the balanced side. However, in practice, there will be signal losses, and this will vary based on the frequencies.
Additionally, some test cases and results with different DAC Vop settings is also mentioned in the attached “ADC-DAC-PWR.pdf” for reference.
Reference Link:
ADC-DAC-PWR.pdf (299.4 KB)
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