Does the PCIe IP run through NoC or PL? Is there an example design for G57D?

The PCIe is implemented through NoC. Validated PCIe Gen4x4 as both Endpoint (EP) and Root Port (RP) using the iWave Gen4x8 FMC PCIe module. (https://iwave-global.com/product/pcie-gen4-x8-fmc-module/ )

The example design for the iW-G57 devkit is available at the FTP location, please connect with iWave representative for FTP details.

For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com

Please find the detailed product information here:
Versal™ AI Edge System on Module