If the FPGA DDR memory needs to be removed in the firmware (Quartus/Platform Designer), please ensure the steps below:
- Remove the FPGA DDR signals from the top module (agilex_top.v).
- Remove the IP files related to FPGA DDR from the QSF file.
Since the software components do not rely on FPGA DDR for execution, the same BSP can be used without modifications after removing the FPGA DDR from the Quartus design.
If more memory space is needed on the H2F bridge for custom HDL designs (OCM, drivers etc). In the design example the H2F bridge is used to address the FPGA DDR memories.
Also, if additional memory space on the H2F bridge is needed for other custom HDL designs along with FPGA DDR, you may reduce the H2F bridge memory space to FPGA DDR by modifying the MUX logic used.
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
Agilex™ 7 (R31A/R31B/R31C) SoC FPGA System on Module