Please refer to the AMD forum link below for guidance on resolving the design compilation error.
When routing clocks from global clock (GC) pins to an MMCM, the preferred solution is:
clk_p/clk_n ------> IBUFDS-------> MMCM
since this solution uses a dedicated routing path from the FPGA-pins to the MMCM that maintains clock quality.
However, if your global clock pins are located in one of the special HD banks of UltraScale, then you must use the following sub-optimal solution:
clk_p/clk_n ------> IBUFDS-------> BUFG-------> MMCM because, as described on page 10 of UG572(v1.9), the BUFG is needed for the IBUFDS to reach an MMCM.
Also for this situation, as described on page 10 of UG572, you should place a CLOCK_DEDICATED_ROUTE=FALSE constraint in the project .xdc constraints file to avoid a DRC error.
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Kintex™ UltraScale+™ System on Module