What are the clocking requirements for PCIe Root Port and Endpoint modes?

FPGA Boards & Solutions MPSoC Boards & Solutions
, ,
1

PCIe Clock and reset is taken care in module itself for root port and end point application. Below are the summary details.

Clocking Architecture Overview

  • RootPort Mode (PCIe x8) :
  1. The 100MHz REFCLK for the PCIe x8 connector is generated in the module and routed to pins A13 & A14 of the PCIe connector.
  2. An independent 100MHz REFCLK for the FPGA/MPSoC PCIe bank is also generated in the module and connected to FMC connector B20 & B21 (GBTCLK1_M2C_P & N).
  • Endpoint Mode (x8):
  1. The 100MHz REFCLK from PCIe x8 connector pins A13 & A14 is bypassed directly to FMC pins B20 & B21 (GBTCLK1_M2C_P & N) of the FMC connector for REFCLK of FPGA/MPSoC PCIe bank.

Operational Configurations: Refer PCIe Select Switch for switch selection in PCIe Hardware User Guide.

For further inquiries, please get in touch with mktg@iwave-global.com

Please find the detailed G35D product information in the below link,