What are the steps to resolve the PTP issue on GEM0?

FPGA Boards & Solutions MPSoC Boards & Solutions
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Please follow below steps (provided with images) to resolve the PTP issue on GEM0 in Vivado tool:

  • In Zynq UltraScale+ MPSoC IP, enable GEM0 and configure the MIO pins in the I/O Configuration tab.
  • In the PS-PL Configuration tab, enable the TSU signal for GEM0, along with TSU BUFG and the clock from PL option.

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  • Connect fmio_gem_tsu_clk_from_pl and fmio_gem_tsu_clk_to_pl_bufg in a loopback.

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  • Connect emio_enet0_tsu_inc_ctrl to a Constant IP, and set the constant value to 2 ‘b11 to enable normal timer register increments.

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With the above steps the XSA and the binaries must be re-compiled.

For further inquiries, please get in touch with mktg@iwave-global.com

Please find the detailed G65M product information in the below link,