Zynq™ UltraScale+™ MPSoC Boards & Solutions

ZU7/ZU5/ZU4 A dedicated space for mastering the complex interplay between multi-core software and cost-optimized edge hardware logic. ZU5/ZU4/ZU3T/ZU3/ZU2/ZU1 A dedicated space for mastering the complex interplay between multi-core software and power-conscious hardware logic. ZU19/ZU17/ZU11 A dedicated space for mastering the complex interplay between multi-core software and ultra-high-density custom hardware logic. ZU15/ZU9/ZU6 A dedicated space for mastering the complex interplay between multi-core software and highly optimized custom hardware logic.

Topic	Views	Activity
About the Zynq™ UltraScale+™ MPSoC Boards & Solutions category Zynq™ UltraScale+™ MPSoC Boards & Solutions mpsoc-som	7	May 15, 2026
How to enable FMC+ power using Bare-Metal for ZU11EG SoM? ZU19/ZU17/ZU11 g35m-zu11eg-som , baremetal , enable-fmc-power-in-bare-metal	1	June 9, 2026
What is the IO Voltage on Bank 65 and Bank 66 on ZU3EG? ZU7/ZU5/ZU4 g36m-zu3eg , bank-65-66-io-voltage	3	June 9, 2026
Whether it is possible to configure a different I/O voltage for Bank 94 independently, or is a common voltage mandatory across all banks connected to PMIC LDO4? ZU19/ZU17/ZU11 g35m-zu19eg-som , pmic-ldo4-volatge-configurable	4	June 5, 2026
How is the configuration of the Boot Mode Pins PS_MODE[0:2] and what other boot devices does it support? ZU5/ZU4/ZU3T/ZU3/ZU2/ZU1 g36m-zu3eg , boot-mode-switch-settings	2	June 4, 2026
How must the reference clock for the endpoint configuration be sourced on the FMC-to-PCIe Adapter? ZU7/ZU5/ZU4 g30m-zu7ev , end-point-configuration	4	June 2, 2026
Can FMC to PCIe Adapter 1 GBTCLK0_M2C (100 MHz) be used to drive GTH223 REFCLK0 for the PL side xDMA (PCIe x2) Root Port? ZU7/ZU5/ZU4 g30m-zu7ev , g42m-zu49dr , g35m-zu19eg-som , fmc-to-pcie-adapter	2	June 2, 2026
What license is required for generating the bitstream while using JESD IPs? ZU19/ZU17/ZU11 g35d-dev-kit , g35m-zu19eg-som , jesd-ip-license	7	May 26, 2026
How the PMIC LDO1 and LDO4 are configured in G35M ZU11EG SoM ZU19/ZU17/ZU11 g35m-zu11eg-som , pmic-ldo1-and-ldo4-configuration	4	May 26, 2026
How the FMC I2C lines are connected from the I2C Mux Switch settings in G35D ZU11EG? ZU19/ZU17/ZU11 g35m-zu11eg-som , i2c-mux-settings	3	May 26, 2026
What are the different methods to program eMMC? ZU19/ZU17/ZU11 g35m-zu11eg-som , emmc-programming-methods	5	May 25, 2026
How to make sure if all the images are avaialble in eMMC? ZU19/ZU17/ZU11 g35d-dev-kit , g35m-zu19eg-som , images-in-emmc	2	May 25, 2026
What is the use of CVE check? Zynq™ UltraScale+™ MPSoC Boards & Solutions cve-check , g35m-zu19-zu17-zu11 , g30m-zu7-zu5-zu4 , g65m-zu15-zu9-zu6 , g36m-zu5-zu4-zu3t-zu3-zu2-zu1	1	May 25, 2026
Can VCU take video input stream directly on the fly and what is the command for the processed VCU? ZU7/ZU5/ZU4 g30m-zu7ev , vcu-input	2	May 25, 2026
What is the functionality of SI5341B-D-GM clock synthesizer chip used in G30M/G30D? ZU7/ZU5/ZU4 g30m-zu7-zu5-zu4 , g30d-devkit , si5341b , clock-synthesizer-chip	6	May 18, 2026
What are the FPGA pins that support 300MHz clock input to on G30M/G30D? ZU7/ZU5/ZU4 g30m-zu7-zu5-zu4 , g30d-devkit , 300mhz-clock	7	May 18, 2026
What are the FPGA pins that support 100MHz clock input to G30M/G30D? ZU7/ZU5/ZU4 g30m-zu7-zu5-zu4 , g30d-devkit , 100mhz-clock	3	May 18, 2026
How to change the default IO voltage for Bank46 on the ZU3EG variant of the iW-G36M SOM? ZU7/ZU5/ZU4 g36m-zu3eg , change-io-voltage-bank-46	8	May 8, 2026
What is the solderable spacer part, its manufacturer and its recommendations? ZU7/ZU5/ZU4 g30m-zu7-zu5-zu4 , solderable-spacer	5	May 8, 2026
What is the HD Bank IO levels of G35M ZU19/ZU17/ZU11 SOM and can it be configured in software? ZU19/ZU17/ZU11 g35m-zu19eg-som , g35m-zu11eg-som , g35m-zu17eg-som	5	May 6, 2026
How to switch from sysvinit to systemctl in the rootfs in G35M MPSoC SOM? ZU19/ZU17/ZU11 g35m-zu19eg-som , sysvinit-to-systemd	6	May 4, 2026
What are the U-Boot commands to initialize and start an SD boot on iWave SOM? ZU19/ZU17/ZU11 g35m-zu19eg-som , commands-boot-from-uboot	8	April 30, 2026
What are the steps to be followed to add the .bit file to the boot image? ZU19/ZU17/ZU11 g35d-dev-kit , g35m-zu19eg-som , add-bit-file	5	April 30, 2026
How to locate and control the PMOD GPIOs on the G35D devkit within the Zynq UltraScale+ MPSoC environment? ZU19/ZU17/ZU11 g35m-zu19eg-som , g35d-devkit , pmod-gpio	11	April 24, 2026
How much should the reference clock be configured in G65D devkit and is it possible to program the clock synth? ZU15/ZU9/ZU6 g65m-zu15eg-som , g65d-dev-kit , clock-synthesizer-file , vivado-constraint-file	4	April 24, 2026
Which is the clock generator used in G36M & what are different variants with a lower power clock generator compatible for G36M? ZU5/ZU4/ZU3T/ZU3/ZU2/ZU1 clock-generators , g36m-zu3eg	2	April 24, 2026
How to configure the clocks to support 10G Ethernet without adding FMC cards? ZU7/ZU5/ZU4 g65m-zu15eg-som , g65d-dev-kit , g30m-zu5ev	7	April 22, 2026
What is the detailed clock distribution architecture of the G30M SOM, specifically regarding the PS and PL reference clocks and the source for the PCIe bridge? ZU7/ZU5/ZU4 g30m-zu7-zu5-zu4 , clock-sources , ps-gtr-and-pcie-bridge-clock	6	April 20, 2026
Does G35M SOM support BBRAM? Is there an application note for BBRAM? ZU19/ZU17/ZU11 g35m-zu19eg-som , bbram-implementation	4	April 20, 2026
What command is used to check the kernel clk_summary if refclk prints are missing during boot? ZU7/ZU5/ZU4 g30m-zu7-zu5-zu4 , boot-banner-refclk-prints	5	April 20, 2026