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Whether it is possible to configure a different I/O voltage for Bank 94 independently, or is a common voltage mandatory across all banks connected to PMIC LDO4?
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0
|
22
|
June 5, 2026
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Can FMC to PCIe Adapter 1 GBTCLK0_M2C (100 MHz) be used to drive GTH223 REFCLK0 for the PL side xDMA (PCIe x2) Root Port?
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0
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8
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June 2, 2026
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What license is required for generating the bitstream while using JESD IPs?
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0
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50
|
May 26, 2026
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How to make sure if all the images are available in eMMC?
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0
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18
|
May 25, 2026
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How to switch from sysvinit to systemctl in the rootfs in G35M MPSoC SOM?
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0
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27
|
May 4, 2026
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What are the U-Boot commands to initialize and start an SD boot on iWave SOM?
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0
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34
|
April 30, 2026
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What are the steps to be followed to add the .bit file to the boot image?
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0
|
26
|
April 30, 2026
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How to locate and control the PMOD GPIOs on the G35D devkit within the Zynq UltraScale+ MPSoC environment?
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0
|
30
|
April 24, 2026
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Does G35M SOM support BBRAM? Is there an application note for BBRAM?
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0
|
16
|
April 20, 2026
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How to clean the FSBL firmware build and is it possible to provide work directories for pmufw, atf and u-boot?
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0
|
31
|
April 17, 2026
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How to remotely update the ZU19EG firmware (either bistream, BOOT files or rootfs) via ethernet interface in G35D?
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0
|
28
|
April 12, 2026
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How to load Vivado ML Enterprise License Edition?
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0
|
203
|
April 1, 2026
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How would to add arguments to the boot command while isolating core 3 in the yocto image?
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0
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21
|
March 30, 2026
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How to build the image(s) with a read-only file system in G35M SOM?
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0
|
20
|
March 30, 2026
|
|
How to obtain the required Vivado license to proceed with G35D development kit?
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0
|
31
|
March 28, 2026
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While building a custom bitstream, why does the Xilinx IP shows that the license is only available for simulation?
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0
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17
|
March 27, 2026
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What is the resistor value of VRP pin G35M SOM?
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0
|
19
|
March 19, 2026
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How to solve the Boot Issues while booting from SD Card using G35M SOM?
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0
|
30
|
March 18, 2026
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|
What is the solution when G35M gets stuck after loading BL31 in the Petalinux?
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0
|
21
|
March 16, 2026
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Is it advisable to leave SD1_PWR & SD_CD left unconnected?
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0
|
19
|
March 14, 2026
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|
What is the SW6 Switch settings for connecting to the board via JTAG Cable?
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0
|
20
|
March 14, 2026
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|
What is the supported voltage and the current drawn in VRTC pin, G35M SOM?
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0
|
16
|
March 13, 2026
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|
Which clock is an input to G35D and which is an output from G35D via the FMC/FMC+?
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0
|
18
|
March 11, 2026
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Which lane of PS-GTR is used for the USB0 in G35D Development kit?
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0
|
25
|
March 7, 2026
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|
What are the configurations for Low power consumption in G35M SOM?
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0
|
35
|
February 7, 2026
|
|
How does the POR sequence delay impact the BootROM SD card initialization timeout on the Zynq UltraScale+ MPSoC?
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|
0
|
60
|
February 7, 2026
|
|
What is the footprint compatibility for SD card level translator NVT4857 vs TXS0206?
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|
0
|
32
|
February 7, 2026
|
|
What are the minimum required signals on B2B connectors that are needed for FPGA to function?
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|
0
|
36
|
February 7, 2026
|
|
What are the pinout differences of Samtec Firefly ECUO vs. PTMO & PCB routing optimization for firefly connector?
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|
0
|
61
|
February 7, 2026
|
|
What is the maximum VCCIO current available for Banks 67 & 68 on G35M SOM?
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|
0
|
30
|
February 7, 2026
|