In G35D Devkit, lane2 is selected (SW6 - Bit3 - ON) for USB0 and refclk2 (52MHz), which is sourced from the clock synthesizer OUT3.
Please make sure to properly configure the clock synthesizer, refclock & Input freq (Vivado) and the lane in dts & hardware. Configuring the clock synthesizer is done in FSBL (refer the FSBL patch) and for clock customization refer section Clock Synthesizer from the software user guide.
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Please find the detailed product information here:
Zynq™ UltraScale+™ ZU19/ZU17/ZU11 MPSoC System on Module