The 300 MHz input clock is generated from the on-SOM oscillator and connected to Bank 65 general-purpose clock input pins. This clock is used as the LVDS reference clock for the PL DDR4.
For more details, please refer to section “MPSoC Reference Clock”, in the latest SOM datasheet.
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Please find the detailed product information here:
Zynq™ UltraScale+™ ZU7/ZU5/ZU4 MPSoC System on Module