What are the troubleshooting timing violations on internal FPGA logic clocks and how to resolve the issue in the fabric clock domain?

Virtex & Kintex Boards & Solutions Kintex™ UltraScale+™: KU19P
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Our findings indicate that the error is specific to designs containing an ILA (Integrated Logic Analyzer). It seems to occur when Vivado attempts to recover certain clock parameters (skew, period, etc.) but unable to find the original clock settings.

To resolve this, please add the clock constraint in XDC file:

create_clock -period 10.000 -name clk_in -add [get_ports clk]

Parameters:

  • -period 10.000: Defines the clock period in nanoseconds (e.g., 10.000 ns = 100 MHz).

  • clk_in can be renamed to any identifier you prefer (ensure the same name is used in your logic and when connecting the clock to the ILA).

  • clk is the port through which the clock signal enters the FPGA.

After applying this constraint, re-run the synthesis and implementation.

Note: In higher Vivado versions, AMD has fixed.

For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com

Please find the detailed product information here:
Kintex™ UltraScale+™ System on Module