iWave has verified both the clocking configurations.
- If using FPGA design with RFSoC internal PLL is disabled, it is necessary to feed the sampling clock from LMX for ADC and DAC tile.
- Also, if the RFSoC internal PLL is enabled, it is necessary to feed the reference clock from the LMX to SoC ADC/DAC tile reference clock pins.
For more details, please connect with iWave representative to access the latest release notes from the FTP link.
For further product inquiries, please get in touch with our sales team at mktg@iwave-global.com
Please find the detailed product information here:
ZU49/ZU39/ZU29DR RFSoC System on Module