The PS DDR is initialized automatically by the FSBL.
The DDR parameters (timing & memory) are configured in processing_system IP in Vivado tool or pulled from the iWave Board Files.
When the hardware (XSA) is exported, these settings are baked into FSBL Source code. The PS DDR is initialized using the function ‘XFsbl_Initialize’ in the file ‘xfsbl_initialization.c’ of FSBL source.
The FSBL executes this initialization code during the boot sequence. This configures the memory controller registers.
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Please find the detailed product information here:
Zynq™ UltraScale+™ ZU19/ZU17/ZU11 MPSoC System on Module