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Is it feasible to modify the FPGA architecture and generate a revised XSA file for software handoff?
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0
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4
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March 22, 2026
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How is the VPP OTP pin connected in G69M (AM62Lx) OSM SOM?
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0
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5
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March 20, 2026
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How to configure the iWave credentials for AWS in G69M OSM SOM?
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0
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5
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March 20, 2026
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What is the resistor value of VRP pin G35M SOM?
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0
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4
|
March 19, 2026
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How to solve the Boot Issues while booting from SD Card using G35M SOM?
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0
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4
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March 18, 2026
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What is the solution when G35M gets stuck after loading BL31 in the Petalinux?
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0
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7
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March 16, 2026
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Is it advisable to leave SD1_PWR & SD_CD left unconnected?
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0
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3
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March 14, 2026
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What is the SW6 Switch settings for connecting to the board via JTAG Cable?
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0
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6
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March 14, 2026
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What is the supported voltage and the current drawn in VRTC pin, G35M SOM?
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0
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5
|
March 13, 2026
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How to check whether the EDID is assigned correctly in G37M Q7 SOM?
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0
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11
|
March 12, 2026
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What is the specific Vivado license is required to work with the devices in G35D Devkit?
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0
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8
|
March 11, 2026
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Which clock is an input to G35D and which is an output from G35D via the FMC/FMC+?
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0
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5
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March 11, 2026
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How to read SMB_ALERT pin is configured to G27M SOM?
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0
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3
|
March 11, 2026
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Why does G27M/G27D does not power ON/OFF when RTC battery is connected?
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0
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4
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March 11, 2026
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What are the DTSI files that support all the interfaces for G65D Devkit?
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0
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4
|
March 11, 2026
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Which lane of PS-GTR is used for the USB0 in G35D Development kit?
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0
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9
|
March 7, 2026
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Why does the Boot from SD Fail with G30D Devkit? Is there an Errata?
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0
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55
|
February 11, 2026
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What are the configurations for Low power consumption in G35M SOM?
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0
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21
|
February 7, 2026
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How does the POR sequence delay impact the BootROM SD card initialization timeout on the Zynq UltraScale+ MPSoC?
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0
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23
|
February 7, 2026
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What is the footprint compatibility for SD card level translator NVT4857 vs TXS0206?
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0
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17
|
February 7, 2026
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What are the minimum required signals on B2B connectors that are needed for FPGA to function?
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0
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14
|
February 7, 2026
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What are the pinout differences of Samtec Firefly ECUO vs. PTMO & PCB routing optimization for firefly connector?
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0
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18
|
February 7, 2026
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What is the maximum VCCIO current available for Banks 67 & 68 on G35M SOM?
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0
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14
|
February 7, 2026
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What is the PMOD voltage level in G35M Devkit?
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0
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17
|
February 7, 2026
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What are the timing requirements for SD card boot in G35M MPSoC SOM?
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0
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16
|
February 7, 2026
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What is the Power Requirements for PCIe Endpoint Mode using G35M SOM?
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0
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19
|
February 7, 2026
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What are the clocking requirements for PCIe Root Port and Endpoint modes?
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0
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15
|
February 7, 2026
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Why does Vivado custom memory part CSV produce a “out of date” issue with Windows PC?
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0
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16
|
February 7, 2026
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Which IO can be configued for PCIe Reset in G35M SOM?
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0
|
14
|
February 7, 2026
|
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Can the REFCLK_CH1 output from the Clock Synthesizer be shared with REFCLK_CH0?
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0
|
14
|
February 7, 2026
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