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What are the timing requirements for SD card boot in G35M MPSoC SOM?
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0
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16
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February 7, 2026
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What is the Power Requirements for PCIe Endpoint Mode using G35M SOM?
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0
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19
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February 7, 2026
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What are the clocking requirements for PCIe Root Port and Endpoint modes?
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0
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15
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February 7, 2026
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Why does Vivado custom memory part CSV produce a “out of date” issue with Windows PC?
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0
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16
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February 7, 2026
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Which IO can be configued for PCIe Reset in G35M SOM?
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0
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14
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February 7, 2026
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Can the REFCLK_CH1 output from the Clock Synthesizer be shared with REFCLK_CH0?
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0
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14
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February 7, 2026
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How the JTAG signals in the FMC 'one-to-one' cable should be isolated?
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0
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11
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February 7, 2026
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Are the boot media pins connected to the Board to Board Connector?
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0
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13
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February 7, 2026
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What is the maximum operating temperature for Zynq UltraScale+ ZU19EG MPSoC SOM?
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0
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12
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February 7, 2026
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Are PL DDR4 pinouts are available in IO_constraints.xdc?
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0
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12
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February 7, 2026
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How much current can the 5V Fan output provide on the ZU19EG G35M SOM?
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0
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10
|
February 7, 2026
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Can G35M SOM can communicate with G30M SOM over PCIe link?
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0
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13
|
February 7, 2026
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How the clock initialization & DTS are configured in G35M SOM?
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0
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15
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February 7, 2026
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What is the configuration of PUDC_B pin on G35M & G30M SOM?
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0
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18
|
February 7, 2026
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Is the FMC board compatible with Xilinx Evaluation Board VCU108?
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0
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19
|
February 7, 2026
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Is the Environment testing & Conformal Coating done with G30M SOM series?
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0
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10
|
February 7, 2026
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What are the additional settings required to change the Boot Mode to JTAG mode in G30M SOM?
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0
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8
|
February 7, 2026
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Is the PS-GTR Reference Resistor (PS_MGTRREF) present in G30M ZU7EV SOM?
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0
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14
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February 6, 2026
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What is the HP Bank Voltage for Banks 64 & 66 in G30M ZU7EV SOM?
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0
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14
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February 6, 2026
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What are the MIPI CSI D-PHY Configuration (HP Banks) in iG-G30M ZU7EV SOM?
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0
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12
|
February 6, 2026
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What are the Ethernet Interface and Magnetics Configurations for the G35D Devkit?
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0
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12
|
February 6, 2026
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Can JTAG-HS2/HS3 cable be connected to G35M SOM?
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0
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11
|
February 6, 2026
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What is the PCIe x8 Gen3 FMC Module: Mode & Lane Configuration in G35D DevKit?
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0
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14
|
February 6, 2026
|
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Is JTAG_TRST Signal supported in Zync UltraScale+ MPSoC ZU11/17/19EG G35M SOM?
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0
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11
|
February 6, 2026
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What are the dimensions of Power Jack, SIM Connector & Storage Interface used in G36S SBC?
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0
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12
|
February 6, 2026
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Is the bench power supply of 5V/5A input enough for G35M ZU19EG SOM?
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0
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8
|
February 6, 2026
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What is the use of SI5341 Clock Synthesizer in G35D DevKit?
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0
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12
|
February 6, 2026
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What are the different LED status available in G35M, G30M & G36S Zync UltraScale+ MPSoC SOM?
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0
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16
|
February 6, 2026
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What type of vias and PCB material is used in iG-G35M SOM?
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0
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12
|
February 6, 2026
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How to change the I/O voltage of LDO after boot?
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0
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9
|
February 6, 2026
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